Typically, a computer system contains a processor, a bus, and other peripheral devices. The processor is responsible for executing instructions using the data in the computer system. The bus is used by the microprocessor and the peripheral devices for transferring information between one another. The information on the bus usually includes data, address and control signals. The peripheral devices comprise storage devices, input/output I/O devices, etc. Generally, all operations being performed in the computer system occur at the same frequency.
The microprocessor has a core for processing the data. Since generally all operations performed by the computer system occur at the same frequency, the logic operations performed by the core are at the same frequency as the transfer of data, address and control signals on the computer system bus.
Some logic operations performed by the core, such as arithmetic operations, require multiple cycles to complete. During completion of these multiple cycle operations, the bus remains idle. It is desirable to have the core operate at a faster speed than the bus, so that operations are performed more quickly. In this manner, the bus will be used more frequently, such that bus idle states will be reduced and operations performed more quickly.
Many techniques exist to reduce the power consumed by the processor. One technique for this has been to stop the processor regardless of the current instruction being executed. Methods have been employed whereby the processor is stopped on predetermined conditions. Another mechanism used in the prior art causes the processor to stop asynchronously by disabling the externally generated clock signal utilized to generate the internal clock of the device.
A problem with asynchronously disabling the external reference frequency generator involves the fact that most microprocessors and computer systems utilize a phase-locked loop (PLL) circuit to multiply the reference frequency by some factor to generate the system's internal clock rate. The internal clock signal is utilized by the central processing unit (CPU) of the computer during the execution of its various functions and instructions. A problem arises is that if the clock is stopped externally, then the internal phase-locked loop circuitry is likewise disabled. Under such circumstances, re-enabling the external reference frequency does not produce an instantaneous response from the PLL. In other words, the PLL requires some fixed time period (e.g., hundreds of milliseconds) to stabilize and achieve lock. During this start-up time period, spurious signals and glitches are commonly generated, leading to unpredictable results. Thus, starting and stopping of the processor's clock by disabling the external reference input frequency results in a loss of pseudo-instantaneous response. What is needed is a means for reducing power consumption in a processor which does not cause a PLL in a computer system to become unstabilized, such that spurious signals and glitches result. That is, it is desirable to have a mechanism for reducing power in a processor which can be utilized such that the remainder of the computer system is unaware of its use (i.e., it is transparent).
Many of today's processors include a small on-chip memory used to temporarily store data and instructions for use by the processor. These small on-chip memories are referred to as caches. The data in the cache represents a portion of the data in the main memory. If the data is changed in the main memory, data in the cache may no longer be current. In the prior art, where data in the cache is no longer current, it is invalidated. This invalidation is performed to ensure that the processor only receive data from the cache which is current. This is referred to as cache coherency. Often the invalidation is no more than setting or resetting a bit in the cache corresponding to the storage location of the invalid data.
Problems exist where a microprocessor which includes a cache is powered down or placed in a state of lower power consumption. One problem occurs where an access is made to the memory while the processor is in the reduced power consumption state. In this situation, the processor is unable to invalidate data in the internal cache to maintain cache coherency. Therefore, when the processor returns to the powered up state, it may use invalid data. Various prior art solutions have been employed to address this problem. One prior art solution is to flush the cache before entering the low power down state, so that all the data in the cache is marked as invalid. The other solution is to flush the cache immediately upon powering up. Flushing the cache results in a large performance penalty in that the processor is unable to execute any instructions because there is no data or instructions in the cache. Therefore, if the cache has been flushed, the processor is delayed the amount of time necessary to obtain data and instructions from memory. It is desirable to avoid having to flush the cache when entering or executing a powered down state. Similarly, it is desirable to maintain cache coherency in a low power state.
When additional features are integrated in a microprocessor, its use most often requires changes to the computer system to accommodate the new features. These changes could take the form of modifications to the circuit board, including adding extra circuitry. Ideally, new features and faster processing should be added without changing, for example, the mother board of a computer system. It is thus advantageous to modify microprocessors by incorporating new features in such a way as to reduce or dispense with changes to the remainder of the computer system. It is also advantageous to keep the number of hardware changes small so that preexisting computer applications can benefit by upgrading their computer systems without having to acquire new system components, thereby avoiding huge expenditures.
The present invention provides a means for invalidating lines in a cache when in a non-clocked low power state.